Midgard researchers have been included in a volume of retrospectives on research into computer architecture.

The International Symposium on Computer Architecture is the premier forum for new ideas and experimental results in computer architecture, with this year marking the Symposium’s 50th anniversary.

As part of the celebrations, significant and memorable papers from 1996 to 2020 were selected for a 50th anniversary volume of articles, telling a story of how research at ISCA has progressed over those twenty-five years. Each article was accompanied by a retrospective from the authors.

Scale-out processors introduces the first generation of cloud-native CPUs, and is authored by Babak Falsafi and members of his Parallel Systems Architecture Lab, including Boris Grot of Midgard. Based on a metric of performance-density, the authors present a framework to optimize the amount silicon required in a server CPU to support software services in the datacenter while maximizing throughput and maintaining end-to-end service latency guarantees. This research created the blueprint for an ARM-based server CPU, Cavium ThunderX.

Also included in the volume of retrospectives, co-authored by Babak Falsafi, is Dead-block prediction & dead-block correlating prefetchers, a paper published in 2001 that targeted bridging the growing performance gap between processors and memory (known at the time as the “Memory Wall”). It proposes CPU predictors that accurately identify ‘when’ a memory block on-chip becomes evictable and ‘what’ subsequent memory block to prefetch and hide long memory access latency. The lasting impact of this work has been to inspire memory streaming technologies called temporal streaming that have appeared in products including IBM BlueGene/Q and ARM Neoverse N2.

Abhishek Bhattacharjee appear as co-author of Hardware-software co-design for brain-computer interfaces, from 2020. This paper presents HALO (Hardware Architecture for LOw-power BCIs), a general-purpose architecture for implantable brain computer interfaces. HALO enables tasks such as treatment of disorders (e.g., epilepsy, movement disorders), and records/processes data for studies that advance our understanding of the brain.

Prof. Bhattacharjee is also lead author of 2009 paper Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors. The technology presented in this paper claimed to improve Intel’s Threading Building Blocks (TBB) parallel runtime system by implementing task stealing techniques, using a criticality predictor to reduce load imbalance. It also suggested using criticality prediction to guide dynamic energy optimizations in barrier-based applications, achieving average energy savings of 15%.

The final number of papers selected was more than twice than in the Symposium’s previous retrospective, reflecting the growth of the computer architecture research community in the past 25 years. Close to 5% of this computer architecture research is related to EPFL. Organizers hope this retrospective volume is an exciting read for older and younger generations of computer architects.

  • Author: Tanya Petersen
  • Image: © iStock / EPFL 2023
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